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[Com Port] SPI_ram

Description: verilog读写RAM的程序 verilog读写RAM的程序-this is a program of that reading or writting a ram.
Platform: | Size: 11264 | Author: 单 | Hits:

[Program doc] rs232_des

Description: uart verilog code using ram and a-uart verilog code using ram and all
Platform: | Size: 21504 | Author: ds venki | Hits:

[VHDL-FPGA-Verilog] HWL_ASYNC_FIFO_DRAM_BA

Description: asynchronous fifo based on distributed RAM. xilinx fpga. VErilog language.
Platform: | Size: 2048 | Author: D | Hits:

[VHDL-FPGA-Verilog] video_center_scan_scaler_alpha_blend

Description: 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discription
Platform: | Size: 8481792 | Author: 冰凝 | Hits:

[source in ebook] SDRAM_interface

Description: SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a refresh timer)
Platform: | Size: 2048 | Author: bryan | Hits:

[VHDL-FPGA-Verilog] ram_3

Description: RAM的verilog描述，包含向量名定义，顶层设计等等的精确描述-RAM in verilog description, including vector name is defined, an accurate description of the top-level design, etc.
Platform: | Size: 1024 | Author: micheal zhang | Hits:

[VHDL-FPGA-Verilog] sp6ex18

Description: 基于Verilog HDL的对片内RAM进行连续读写测试实例-Based on the on-chip RAM for continuous reading and writing test cases for Verilog HDL
Platform: | Size: 5089280 | Author: liu | Hits:

[Other] gds8k_32bit_1M

Description: 一款SRAM的verilog代码及版图信息-verilog codes and layout information of a RAM
Platform: | Size: 1056768 | Author: 高翔 | Hits:

[VHDL-FPGA-Verilog] IIC

Description: Verilog IIC程序，RAM接口，方便调试，一主多从-Verilog IIC program, RAM interface, easy to debug, and more a master
Platform: | Size: 1024 | Author: 吴洋 | Hits:

[VHDL-FPGA-Verilog] ahb_ebc

Description: Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
Platform: | Size: 10240 | Author: scnn86 | Hits:

[VHDL-FPGA-Verilog] ram_2

Description: 双端口RAM，可读，可写，用Verilog编写。希望与大神交流，求大神指正。(Dual port RAM, readable and writable, written in Verilog. Hope to communicate with great God, ask God to correct me)
Platform: | Size: 11412480 | Author: 么么哒哈123 | Hits:

[Documents] New WinRAR ZIP archive

Description: verilog coge for ram 64 bit
Platform: | Size: 20480 | Author: swas | Hits:

[VHDL-FPGA-Verilog] cpu_me

Description: 采用verilog编写的cpu,modelsim仿真均实现8条指令功能，有虚拟ram和rom(Using verilog prepared cpu, modelsim simulation functions are to achieve eight instructions, there are virtual ram and rom)
Platform: | Size: 68608 | Author: 王乐 | Hits:

[Education soft system] Domain Specific Hardware Accelerators: Vector Processing Units

Description: This repository contains the source code for VLSI CAD Project, Domain Specific Hardware Accelerators, as apart of coursework in CS6230 : CAD for VLSI. Fall, 2020. What does this repo enclose? Overview The following components are implemented in Bluespec System Verilog: CPU RAM Bus Vector Processor CPU A minimal 2 stage pipelined inorder processor. Vector Processor A vector processor capable of: Vector Negation (int8, int16, int32, float32) Vector Minima (int8, int16, int32, float32)
Platform: | Size: 3301613 | Author: nalevihtkas | Hits:
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